In late '23, we have secured more funding from the NLnet Foundation alowing us to continue our work on Verilog-AMS support. We will work on three tasks. The first two will advance the model compiler and simulator, the third task will involve other projects with a focus on interoperability.
Each task has 5 milestones. Here we will give details and keep track of our progress.
We have implemented the ground node declaration, hierarchical system parameters such as $mfactor. The “ac_stim” function and noise sources are ready for use in small signal analysis. Frequency domain waveform filters (laplace) and discrete filters (inverse-z) are now available for use in behavioural models. The $discontinuity function has been implemented. We have considered “generate struct” some preparations in the code generator have been made.
User defined primitive (UDP) sequential logic modelling with “table” is ready for use. These introduce the foundational discrete modelling features. This milestone is somewhat analogous to the implementation of partial derivatives and “analog function” in the previous project.
We have added syntactic support for basic digital functionality. Made preparations for discrete disciplines, various types of wires, discrete math. “connectmodule”. This work has been delayed by task 2b, as it relies on typed nodes and connect rules.
We have implemented analog events. Cross event, timer event, above event are ready for use. Such events will be used in the “always” blocks and will interact with discrete digital models. We have implemented state variables required in digital models
We have implemented an interface exposing the linear solver and developed a new sparse version of the bump and spike data structure. A new selective trace algorithm improves the performance of simulation with discrete parts.
We have revisited the the data structures behind the connectivity graph. The algorithm that allocates nodes is now based on a hierarchical union-find algorithm. It allows the contraction of nets, global nodes (such as ground), and to keep track of node types. This will be needed both to apply connectrules resolving the final type(s) of a node to place connect modules and to allow for “split” nodes.
Language support for “connectrules” block and “connect” statement have been delayed by the node rework. There is a draft implementation making a distinction between “discrete”, “continuous” and “hybrid” nodes, and selects what is needed in a given hierarchical circuit. Here, “hybrid” nodes are the traditional take on connect modules. They will have to be replaced by two nodes of the effective disciplines and a connect module across.
The event queue has been updated to queue events for specific devices
rather than just global events.
Fanout fanout lists have been implemented, and a trace based recursive tr_advance routine significantly reduces
the number of iterations in mixed signal simulations. See trace-4 branch.
During the work in 2c we have identified an effective method to order nodes along the signal path. This ordering will also be applied to the continuous nodes associated with a matrix entry. It will effectively improve the LU decomposition performance by means of better exploitation of the partial updates.
We have designed a new hierarchical data structure for parameter sets shared across devices. This will allow the efficient storage of hierarchical system parameters, and the use of paramset blocks without much overhead.
The spice wraper how supports models from the current version of ngSpice. These are now available as plugins. The new wrapper accounts for node contractions used in newer models, and now also exposes noise models implemented for Spice. The interface for noise modelling was added to Gnucap to enable Verilog-AMS noise functions (c.f. task 1a). Users may now pick from a larger set of models from different Spice implementations and their variants.
Instead we have explored how to convert circuits written for (a) Spice into portable Verilog-AMS models. This could solve the lock-in problem that normally comes with Spice, since no two Spice implementations share the same input language. In addition, we have explored a method to feed standardised circuits and schematics (from 3b) into a Spice simulator.
For data transfer between applications, a common file format is useful. We have studied formats from different applications centered at schematics and propose a standard file format, “Verilog-S”, for storing schematics. We have produced documentation, and practical information about the translation between Verilog-S and two common schematic file formats.
In parallel to the documentation from 3c, we have developped a Gnucap extension to support gEDA/Lepton schematics and we have upgraded the schematic file format in Qucs to Verilog-S. We did not get to layout yet. It is now possible to effectively use/study/analyse/modify circuits drawn with either lepton-schematic or Qucs.
We have maintained, updated, and extended various Gnucap related projects making use of new features in Gnucap, mostly related to new Verilog-AMS features. For example, more devices in Qucs are now backed by Verilog-AMS electrical models, including more RF devices and Qucs style small signal noise sources. The pole-zero analysis in gnucap-python has been confirmed to work with Verilog-AMS frequency domain models.