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gnucap:start - refer to tarballs on codeberg. no longer on savannah

Gnucap is the GNU Circuit Analysis Package Gnucap is a modern post-spice circuit simulator with several advantages over Spice derivatives. Gnucap and Modelgen-Verilog support a reasonable subset of Verilog-A, for both structural and behavioural analog/mixed models. Work towards Verilog-AMS with NLnet funding is ongoing.

gnucap:manual:tech:white_and_black_space - illustrate more compact spacing

Neither white nor black space has any function, but it is used to arrange characters on the screen, and/or make your code easier to read. Such characters are space, tab and newline. Do not use carriage return or other fancy stuff. On this page, we summarise the most important rules. If there are violations in the code, they should be fixed when the code is edited. Ideally this happens for some other reason.

gnucap:manual:tech:test_macros - add assert, expand on untested

Test Macros Gnucap supplies a set of test macros in the file gnucap/io_trace.h . This file may be included more than once, at any place in the code, to change the options. All of these macros do nothing when compiled with default settings. They exist so they can be left in the code and enabled or disabled as needed by developers without burdening end users with their clutter.

gnucap:manual:commands - add attach

Gnucap commands are defined by plugins. This section defines all commands supplied in the main tarball. Your installation may not have all of these commands, and may have others in addition to these. It depends on which plugins you have installed.

gnucap:manual:commands:attach - created

Purpose Load a plugin, or a set of plugins. Syntax {attach|load} [options] path Comments A file or directory is specified using a path. A path starting with / is absolute. A path starting with . is relative to the current working directory. Other paths refer to the first hit relative to a directory listed in GNUCAP_PLUGPATH.

gnucap:manual:tech:spice2verilog - hsp and uic

Porting/Converting Spice to Verilog(-AMS) Verilog-AMS has been designed to coexist with Spice, and to replace it as needed (among other things). Citing from Annex E of the language reference manual, Analog simulation has long been performed with SPICE and SPICE-like simulators. As such, there is a huge legacy of SPICE netlists. These are supposed to retain its use when upgrading a SPICE simulator. On the other hand, Annex E provides a list of “SPICE primitives” that facilitate the rewrite of ba…

gnucap:manual:languages:spice - spice update and reference verilog

SPICE has irregular and confusing syntax. The preferred way to use SPICE netlists is through subckt declarations. A subckt declaration creates a type that can be used in any language. Case sensitivity can be enabled (default is off in Spice), in order to avoid problems later, when the netlist is expanded.

gnucap:manual:languages:verilog - update

WARNING, TRANSITION In order to get the most up-to-date verilog experience, you should use the Verilog language implementation from modelgen-verilog. See “Status” below. END WARNING The Verilog language plugin attempts to support the syntax of the Verilog-AMS language.

gnucap:manual:tech:plugins:devices:allocation_and_setup - common comparison operators

Implementation Allocation and setup default constructor A default constructor is required. It is used to construct the static object that is registered with the dispatcher. It should do what a default constructor usually does. copy constructor A copy constructor is required. Most objects are created by the copy constructor, as copies of the object registered with the dispatcher. Usually, it should do a SHALLOW copy. In particular, a COMMON should be linked and not copied. A copy const…

gnucap:manual:tech:style - reference white and black space

This section provides guidelines for programmers. Some of them are arbitrary. Please follow them for consistency. If you prefer a different way, please consider that it would be much worse to deal with a dozen different ways in the same body of code.

gnucap:user:netlist_import_and_export:qucs - [Qucs specific types] add parameters

Import and export: Qucs Verilog schematics There is work in progress to replace the Qucs file format for more transparency, versatility and data exchange based on Verilog. See for the current status.

gnucap:user:netlist_import_and_export:geda - [Parameter declarations] add example

The gEDA file format is well known and flexible. Today it is used in Lepton, which provides an editor similar to gschem. A gEDA schematic stores a circuit, and in the proposed format a circuit will be represented as a module. Using Verilog this gives us

gnucap:projects:interface_wrappers - created

Device Interface wrappers, work in progress and questions (c.f. here). * Could the gnucap verilog modelgen be made to target other simulators with enough work or is it very tightly coupled to gnucap internals throughout? For example something like OSDI to replace/supplement OpenVAF in ngspice/vacask?