The Verilog language plugin attempts to support the syntax of the Verilog-AMS language.
Not all features of Verilog-AMS are supported, but those that work will work with Verilog-AMS syntax. Wherever possible, Gnucap features will work in Verilog-AMS mode, even if they don't work in Verilog-AMS.
The Verilog mode is case sensitive, and uses “SI” units.
The “SI” units are case sensitive. 1p is 1e-12. 1P is 1e15. 1m is 1e-3. 1M is 1e6.
Comments are preceded by // and extend to the end of the line.
The format is not line oriented. A semicolon terminates a statement. You can extend a line by ending it with \ .
In gnucap, for now, you must have one statement per line. This is non-standard.
From startup, you can set Verilog mode with the command line:
All components have the same syntax:
type #(arguments) label (port list) ;
resistor #(10K) Rload (out, 0); // one unnamed argument, ports by order resistor #(.r(10K)) Rload (.p(out), .n(0)); // the same component, arguments by name, ports by name
amp #(.rload(100K)) X1 (.out(out), .in(in), .vcc(vc));
There are some components that exploit the syntax in other languages that are not supported in Verilog mode, but you can use them by switching to a mode that does support that syntax.
// vsource #(.dc(15)) Vcc (.p(vc), .n(0)); // Spice-style source arguments are not supported. // vsource #(.ac(1)) Vin (.p(in), .n(0)); // Spice-style source arguments are not supported.
But you can switch modes, to one that does support the syntax:
// assume it is starting in Verilog mode spice * It takes Spice syntax now Vcc (vc 0) dc 15 Vin (in 0) ac 1 * Commands in Spice mode start with a dot. .verilog // Now it is back in Verilog mode.
Two top level blocks are supported: module and paramset.
A “paramset” statement sets parameters based on an existing compiled model. This will be extended to cover all “masters”. It becomes a “master” that can be instantiated later. It is equivalent to a spice ”.model”.
The syntax is:
"paramset" newname itsmaster ";" parameters "endparamset"
paramset gp_npn npn;\ .bf=150;\ endparamset
According to the standard, lines are not significant. In gnucap, for now, all must be on one line or lines extended by ending with “\”.
Note that the parameter syntax in paramset is different from the parameter syntax instantiating a device.
The basic building block is called a “module”. Modules are descriptions of individual components. Gnucap directly supports only the structural subset of Verilog, so a “module” here is equivalent to a Spice “subckt”.
Modules take the form:
module amp (out, in, vcc); parameter rload=10k; resistor #(.r(1M)) Rb1 (base, vcc); // 1 megohm resistor #(.r(100K)) Rb2 (base, 0 ); resistor #(100K) Rc (col, vcc); resistor #(.r(10K)) Re (.p(emit), .n(0)); capacitor #(.c(1m)) Ce (.p(emit), .n(0)); // 1 millifarad capacitor #(.c(1u)) Cin (base, in ); gp_npn Q1 (.c(col), .b(base), .e(emit)); gp_npn Q2 (.c(vcc), .b(col), .e(e2)); resistor #(.r(1K)) Re2 (e2, 0 ); capacitor #(.c(10u)) Cout (e2, out); resistor #(.r(rload))Rload(out, 0 ); endmodule
amp #(.rload(100K)) X1 (.out(out), .in(in), .vcc(vc)); vsource #(.dc(15)) Vcc (.p(vc), .n(0)); vsource #(.ac(1)) Vin (.p(in), .n(0)); resistor #(10K) Rload (out, 0);
The Verilog language has no concept of commands.
In gnucap, commands are executed at top level the same as the native mode.
The current implementation in gnucap is a very preliminary subset.