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gnucap:projects:nlnet:verilogams [2023/01/09 09:11] felixs 2a update |
gnucap:projects:nlnet:verilogams [2023/01/31 08:36] (current) felixs update 2e, dc sweep |
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| == a) Model overloading by name and parameter ranges according to standard. == | == a) Model overloading by name and parameter ranges according to standard. == | ||
| Verilog defines "paramset" as a means to replace model cards known from spice, cf. LRM section 6.4. | Verilog defines "paramset" as a means to replace model cards known from spice, cf. LRM section 6.4. | ||
| - | The standard essentially allows multiple prototypes by the same name with mutually different interfaces (see [[gnucap:manual:languages:verilog#paramset|usage]]), allowing things like [[gnucap:manual:examples:paramset_recursive|recursive models]]. This requires changes to the way device instances are read in and elaborated [[paramset_implementation|read in and elaborated]]. Preliminary code is available [[http://git.savannah.gnu.org/cgit/gnucap.git/log/?h=paramset-13|here]. Some of it has been added to [[https://codeberg.org/gnucap/gnucsator/src/branch/develop|Gnucsator]]. | + | The standard essentially allows multiple prototypes by the same name with mutually different interfaces (see [[gnucap:manual:languages:verilog#paramset|usage]]), allowing things like [[gnucap:manual:examples:paramset_recursive|recursive models]]. This requires changes to the way device instances are read in and elaborated [[paramset_implementation|read in and elaborated]]. Preliminary code is available [[http://git.savannah.gnu.org/cgit/gnucap.git/log/?h=paramset-13|here]]. Some of it has been added to [[https://codeberg.org/gnucap/gnucsator/src/branch/develop|Gnucsator]]. |
| == b) Implement preprocessor, support backtick, macros, conditionals. == | == b) Implement preprocessor, support backtick, macros, conditionals. == | ||
| == c) Add support for "attribute instance". == | == c) Add support for "attribute instance". == | ||
| == d) Provide logic gates as plug-ins, accessible from Verilog netlists. == | == d) Provide logic gates as plug-ins, accessible from Verilog netlists. == | ||
| == e) Refactor internals; make dc sweep work with parameters. == | == e) Refactor internals; make dc sweep work with parameters. == | ||
| - | Historically the dc sweep command only sweeps elements. Currently, in Gnucap sweeping parameters is more tedious than in other simulators. We will adjust and redefine the data path for parameter values [[precalc_last|TODO_IMPL]], and extend the dc command plugin to make use of it. | + | Historically, the dc sweep command only sweeps element values, following other implementations such as Spice 1-3 and Ngspice. We have redefined the data path for parameter values in [[gnucap:manual:tech:plugins:devices:allocation_and_setup|devices]], in particular "precalc_last" and edited simple devices (elements) accordingly. With these changes, we provide parameter sweeps in [[https://codeberg.org/gnucap/gnucsator/src/branch/develop|Gnucsator]], mirroring Qucsator behaviour. We have refactored and adjusted the default [[gnucap:manual:commands:dc|dc]] command plugin and added support for parameter sweeps. Many new tests have been added in the process. |
| == f) Integrate "model card" hierarchy into Verilog language semantics. == | == f) Integrate "model card" hierarchy into Verilog language semantics. == | ||