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gnucap:manual:languages:verilog [2024/01/30 11:47] felixs lang_verilog now in mgsim |
gnucap:manual:languages:verilog [2026/02/11 04:12] (current) felixs update |
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| ====== Language : Verilog ====== | ====== Language : Verilog ====== | ||
| + | |||
| + | |||
| + | **WARNING, TRANSITION** | ||
| + | |||
| + | In order to get the most up-to-date verilog experience, you should use the Verilog language implementation from modelgen-verilog. | ||
| + | See "Status" below. | ||
| + | |||
| + | **END WARNING** | ||
| The Verilog language plugin attempts to support the syntax of the Verilog-AMS language. | The Verilog language plugin attempts to support the syntax of the Verilog-AMS language. | ||
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| The format is not line oriented. A semicolon terminates a statement. You can extend a line by ending it with \ . | The format is not line oriented. A semicolon terminates a statement. You can extend a line by ending it with \ . | ||
| - | |||
| - | In gnucap, for now, you must have one statement per line. This is non-standard. | ||
| From startup, you can set Verilog mode with the command line: | From startup, you can set Verilog mode with the command line: | ||
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| (* type=wirelead, rating="1/4 watt" *) resistor #((* color=red *).r(10K)) Rload ((* up *) out, 0); | (* type=wirelead, rating="1/4 watt" *) resistor #((* color=red *).r(10K)) Rload ((* up *) out, 0); | ||
| - | ====== Top-level blocks ====== | + | ====== The top-level circuit ====== |
| - | Two top level blocks are supported: module and paramset. | + | Unlike Verilog, Gnucap allows device instances at top level, in addition to "paramset" and "model" declarations. |
| + | Right now (Feb 2026), uninstanciated modules do **not** turn into instances automatically. They need to be instanciated explicitly. | ||
| ===== paramset ===== | ===== paramset ===== | ||
| - | ==== new/WIP ==== | ||
| This relates to task 2a in [[gnucap:projects:nlnet:verilogams]]. The following is implemented in the modelgen-verilog package and bundled with the device plugins ("mgsim") therein. See the examples directory in gnucap-modelgen-verilog for various live applications. | This relates to task 2a in [[gnucap:projects:nlnet:verilogams]]. The following is implemented in the modelgen-verilog package and bundled with the device plugins ("mgsim") therein. See the examples directory in gnucap-modelgen-verilog for various live applications. | ||
| - | A "paramset" statement creates a new type from an existing type. It becomes a "master" that can be instantiated later. It is similar to a spice ".model". | + | A "paramset" statement creates a new type from an existing type. It becomes a prototype that can be instantiated later. It is similar to a spice ".model". |
| A paramset must be declared at top level. | A paramset must be declared at top level. | ||
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| resistor #(.r(1)) r2(1, 2); // avoid the overhead | resistor #(.r(1)) r2(1, 2); // avoid the overhead | ||
| endmodule | endmodule | ||
| + | |||
| + | According to the standard, lines are not significant. In gnucap, for now, all must be on one line or lines extended by ending with "\". | ||
| - | ==== current ==== | + | Note that the parameter syntax in paramset is different from the parameter syntax instantiating a device. |
| + | |||
| + | ==== built in paramset (obsolete) ==== | ||
| This description applies to the default plugin included with the Gnucap package, as of August 2023. | This description applies to the default plugin included with the Gnucap package, as of August 2023. | ||
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| endparamset | endparamset | ||
| - | According to the standard, lines are not significant. In gnucap, for now, all must be on one line or lines extended by ending with "\". | ||
| - | |||
| - | Note that the parameter syntax in paramset is different from the parameter syntax instantiating a device. | ||
| ===== module ===== | ===== module ===== | ||
| - | The basic building block is called a "module". Modules are descriptions of individual components. Gnucap directly supports only the structural subset of Verilog, so a "module" here is equivalent to a Spice "subckt". | + | The basic building block is called a "module". Modules are descriptions of individual components. Gnucap directly supports only the structural subset of Verilog, so a "module" here is similar to a Spice "subckt". Use [[gnucap:manual:modelgen-verilog]] to process behavioural models. |
| Modules take the form: | Modules take the form: | ||
| Line 216: | Line 223: | ||
| ====== Status ====== | ====== Status ====== | ||
| - | The current implementation in gnucap is a very preliminary subset. | + | The current implementation or the Verilog language in Gnucap is a work in progress. For a better Verilog experience, use |
| + | the Verilog language plugin from modelgen-verilog. For this, ''load mgsim'' or ''load mgsim/lang_verilog.so'' **before** switching the language to Verilog. Alternatively, invoke Gnucap with | ||
| + | |||
| + | ''$ gnucap -a mgsim --verilog''. | ||
| + | |||
| + | This step will become unnecessary at some point in the future. Remaining caveats (Feb 2026) are | ||
| - | * The "master" must be defined before it is referenced. | ||
| * The devices and commands are whatever gnucap has installed, not necessarily what is defined in any standard. | * The devices and commands are whatever gnucap has installed, not necessarily what is defined in any standard. | ||
| * The circuit must be defined before any commands using it, unless you want to simulate a partial circuit. Scripted and interactive modifications to the circuit are done the way gnucap usually does. | * The circuit must be defined before any commands using it, unless you want to simulate a partial circuit. Scripted and interactive modifications to the circuit are done the way gnucap usually does. | ||
| - | * The main circuit can also be in Verilog syntax. The Verilog standard has no concept of components at top level. | + | * The main circuit can also be in Verilog syntax. The Verilog standard has no concept of components at top level. |
| * To simulate, there must be a component at top level. Uninstantiated modules do nothing. | * To simulate, there must be a component at top level. Uninstantiated modules do nothing. | ||
| - | * Port direction statements like "inout" are not supported. | + | * Overloading does not fully work at top level. |
| - | * Discipline statements like "electrical" are not supported. | + | * Discipline statements like "electrical" are not supported and/or do nothing yet. |
| - | * Some components, and some types of arguments, are not supported in Verilog mode, but you can switch modes at any time. | + | |