* gnucap:user:netlist_import_and_export

gnucap:user:netlist_import_and_export:geda

The gEDA file format is well known and flexible. Today it is used in Lepton, which provides an editor similar to gschem. A gEDA schematic stores a circuit, and in the proposed format a circuit will be represented as a module. Using Verilog this gives us

gnucap:user:netlist_import_and_export:geometry

Verilog-AMS defines hierarchical parameters $xposition and $yposition as well as $angle to express physical location and orientation as on a wafer or PCB. According to the LRM, $angle is supposed to mean “counter-clockwise”. Our interpretation of counter-clockwise follows when choosing the x axis pointing to the right, and the y axis pointing upwards. Now a 90 degree rotation moves the x axis to the y axis, in other words (x,y)=(1,0) to (0,1). Equivalently, the y axis may be thought of as the i…

gnucap:user:netlist_import_and_export:qucs

Import and export: Qucs Verilog schematics There is work in progress to replace the Qucs file format for more transparency, versatility and data exchange based on Verilog. See for the current status.

gnucap:user:netlist_import_and_export:spice

Import and export: Spice Spice is a family of circuit simulators approximately as old as analog circuit simulation. Most electrical circuit models may be understood as fully analog, and in this sense, Spice is capable of simulating most circuit models.