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gnucap:user:netlist_import_and_export [2024/07/30 12:52] aldavis [Mapping to the application] |
gnucap:user:netlist_import_and_export [2024/08/15 22:01] (current) aldavis [Adding physical position] |
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| We have replaced the nodes with nets, which are now first class objects. This will give us a way to represent the interconnect in a schematic drawing or a layout. It also provides essential data to support analysis and simulation of the interconnect. | We have replaced the nodes with nets, which are now first class objects. This will give us a way to represent the interconnect in a schematic drawing or a layout. It also provides essential data to support analysis and simulation of the interconnect. | ||
| - | |||
| Looking at net "b" as an example, it has 3 connections : r1 pin n, p2 pin p, and u1 pin pn. | Looking at net "b" as an example, it has 3 connections : r1 pin n, p2 pin p, and u1 pin pn. | ||
| + | What is a "net"? It depends how you look at it. It could be the lines on a schematic, or the traces on a PC board. If we are doing a Spice-type simulation, we would want to collapse it into a single node. So we might define: | ||
| + | |||
| + | module net (.a(z), .b(z), .c(z), .d(z), .e(z), .f(z)); | ||
| + | endmodule | ||
| + | |||
| + | This definition gives us up to 6 connections (a,b,c,d,e,f) as seen from outside, all connected together internally, which has the effect of collapsing it all down to one. | ||
| ==== Verilog "system" parameters ==== | ==== Verilog "system" parameters ==== | ||
| Line 208: | Line 213: | ||
| We will number the pins, by position, 1, 2, ... Then we use x1,y1, and so on to locate them. Usually one of them is adequate to locate an object. The others can "float", allowing the actual location to be determined by the surroundings. It is permissible to overspecify locations, provided they are self-consistent, and consistent with connections. | We will number the pins, by position, 1, 2, ... Then we use x1,y1, and so on to locate them. Usually one of them is adequate to locate an object. The others can "float", allowing the actual location to be determined by the surroundings. It is permissible to overspecify locations, provided they are self-consistent, and consistent with connections. | ||
| - | Pin numbering starts at 1 (not 0) to be consistent with most IC and connector pin numbering. | + | Pin numbering starts at 1 (not 0) to be consistent with most IC and connector pin numbering. Pin names should be used instead of numbers if the pins have names. |
| - | In addition to the positions, hflip, vflip, and angle are supported. If there is both a flip and an angle, flip will be done first, then angle. | + | In addition to the positions, hflip, vflip, and angle are supported. If there is both a flip and an angle, flip will be done first, then angle. The angle is specified in degrees counterclockwise, but only 0, 90, 180 and 270 are expected to be supported. |
| - | Another attribute named for the specific tool (example: S0_geda) can be used to stash tool specific data that doesn't fit otherwise. This is intended to assist with a translation from this format back to the tool format. Normally, this would be a string containing a composite of the info (S0_geda="5 10 0 0 0 0 1") If more than one string in a scope is needed, suffixes can be used. (S0_geda_color="blue" S0_geda_symbol="resistor-1.sym") These are stored and passed on without any interpretation. | + | Another attribute named for the specific tool (example: ''S0_geda'') can be used to stash tool specific data that doesn't fit otherwise. This is intended to assist with a translation from this format back to the tool format. Normally, this would be a string containing a composite of the info (''S0_geda="5 10 0 0 0 0 1"'') If more than one string in a scope is needed, suffixes can be used. (''S0_geda_color="blue" S0_geda_symbol="resistor-1.sym"'') These are stored and passed on without any interpretation. For a simple symbol substitution, you might just do ''S0_symbol="input"'' so the schematic shows the "input" symbol, overriding "inout", which is there for the simulator. |
| - | module amp (.a(a0), .c(c0)); | + | module amp ( |
| - | (* S0_x1=-5m, S0_y1=0m *) input a0; | + | (* S0_x1=-5m, S0_y1=0m, S0_symbol="input" *) inout electrical .a(a0), // show symbol ";input", but actual port direction is inout |
| - | (* S0_x1=30m, S0_y1=-3m *) output c0; | + | (* S0_x1=30m, S0_y1=-3m *) output electrical .c(c0) // port syntax per SystemVerilog 3.1a, 18,9 |
| + | ); // a and c are pin names, user specified, outside. a0 and c0 refer to the node the pin connects to, inside | ||
| ground g0; | ground g0; | ||
| ground g1; | ground g1; | ||
| - | (* S0_x1=0m, S0_y1=0m *) resistor #(.r(1k)) r1 (.p(a1), .n(b1)); | + | (* S0_x_p=0m, S0_y_p=0m *) resistor #(.r(1k)) r1 (.p(a1), .n(b1)); // by pin name |
| - | (* S0_x1=24m, S0_y1=7m *) resistor #(.r(1k)) r2 (.p(b2), .n(c2)); | + | (* S0_x_p=24m, S0_y_p=7m *) resistor #(.r(1k)) r2 (.p(b2), .n(c2)); |
| - | (* S0_x1=25m, S0_y1=-3m *) opamp741 #(.gain(100k)) u1 (.p(c3), .n(g1), .ps(g0), .ns(b3)); | + | (* S0_x1=25m, S0_y1=-3m *) opamp741 #(.gain(100k)) u1 (c3, g1, g0, b3); // by pin number |
| net a (a0, a1); | net a (a0, a1); | ||
| Line 237: | Line 243: | ||
| * It is ok to locate a node more than once, provided the locations are the same. | * It is ok to locate a node more than once, provided the locations are the same. | ||
| * If locations of the same node are not the same, the tool shall issue a warning, and make a correction to assure connectivity is correct. | * If locations of the same node are not the same, the tool shall issue a warning, and make a correction to assure connectivity is correct. | ||
| - | * Locating one pin of a footprint or symbol determines the location of the symbol or footprint. | + | * Locating one pin (usually pin one) of a footprint or symbol determines the location of the symbol or footprint. |
| * In the above example, the I/O pins and components have been explicitly located. | * In the above example, the I/O pins and components have been explicitly located. | ||
| * The nets have been implicitly located. | * The nets have been implicitly located. | ||
| Line 244: | Line 250: | ||
| The choice of which nodes to locate could have been different. The following example produces exactly the same result. | The choice of which nodes to locate could have been different. The following example produces exactly the same result. | ||
| - | module amp (.a(a0), .c(c0)); | + | module amp (.a(a0), .c(c0)); // port syntax per IEEE 1364-2005 |
| - | input a0; | + | input electrical a0; // a0, not a. a0 is inside the module. a is outside. |
| - | output c0; | + | output electrical c0; // see IEEE 1364-2005 12.3.3 |
| ground g0; | ground g0; | ||
| ground g1; | ground g1; | ||
| Line 261: | Line 267: | ||
| The following example is over determined, but legal, and produces the same result. | The following example is over determined, but legal, and produces the same result. | ||
| - | module amp (.a(a0), .c(c0)); | + | module amp ( |
| - | (* S0_x1=-5m, S0_y1=0m *) input a0; | + | (* S0_x1=-5m, S0_y1=0m *) inout electrical .a(a0), |
| - | (* S0_x1=30m, S0_y1=-3m *) output c0; | + | (* S0_x1=30m, S0_y1=-3m *) output electrical .c(c0), |
| + | ); | ||
| ground g0; | ground g0; | ||
| ground g1; | ground g1; | ||
| Line 279: | Line 286: | ||
| ==== Multiple applications, both layout and schematic ==== | ==== Multiple applications, both layout and schematic ==== | ||
| - | Files can be combined. | + | Markups can be combined. In this example, schematic ''S0_'' and printed circuit ''PC0_'' are combined in a single file. |
| module amp (.a(a0), .c(c0)); | module amp (.a(a0), .c(c0)); | ||
| Line 289: | Line 296: | ||
| opamp741 #(.gain(100k)) u1 (.p(c3), .n(0), .ps(0), .ns(b3)); | opamp741 #(.gain(100k)) u1 (.p(c3), .n(0), .ps(0), .ns(b3)); | ||
| - | (* S0_x0=-5m, S0_y0=0m, S0_x1=0m, S0_y1=0m, PC0_x0=-5m, PC0_y0=0m, PC0_x1=0m, PC0_y1=0m *) net a (a0, a1); | + | (* S0_x1=-5m, S0_y1=0m, S0_x2=0m, S0_y2=0m, PC0_x1=-5m, PC0_y1=0m, PC0_x2=0m, PC0_y2=0m *) net a (a0, a1); |
| - | (* S0_x1=24m, S0_y1=7m *) (* PC0_x1=24m, PC0_y1=7m *) net b (b1, b2, b3); | + | (* S0_x2=24m, S0_y2=7m *) (* PC0_x2=24m, PC0_y2=7m *) net b (b1, b2, b3); |
| - | (* S0_x0=30m, S0_y0=-3m, S0_x2=25m, S0_y2=-3m, PC0_x0=30m, PC0_y0=-3m, PC0_x2=25m, PC0_y2=-3m *) net c (c0, c2, c3); | + | (* S0_x1=30m, S0_y1=-3m, S0_x3=25m, S0_y3=-3m, PC0_x1=30m, PC0_y1=-3m, PC0_x3=25m, PC0_y3=-3m *) net c (c0, c2, c3); |
| endmodule | endmodule | ||
| - | |||
| Portions that apply in only certain contexts can be selectively included with '''ifdef''. This may be useful when the component list needs to be different for the different applications, such as when the nets have different forms for a different route or parameters. Macros like ''%%__S0__%%'' and ''%%__S0__geda__%%'' are automatically predefined if appropriate. These macros should not be defined in the file, except temporarily for debugging. | Portions that apply in only certain contexts can be selectively included with '''ifdef''. This may be useful when the component list needs to be different for the different applications, such as when the nets have different forms for a different route or parameters. Macros like ''%%__S0__%%'' and ''%%__S0__geda__%%'' are automatically predefined if appropriate. These macros should not be defined in the file, except temporarily for debugging. | ||
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| `ifdef __S0__ | `ifdef __S0__ | ||
| - | (* S0_x0=-5m, S0_y0=0m, S0_x1=0m, S0_y1=0m *) net a (a0, a1); | + | (* S0_x1=-5m, S0_y1=0m, S0_x2=0m, S0_y2=0m *) net a (a0, a1); |
| - | (* S0_x1=24m, S0_y1=7m *) net b (b1, b2, b3); | + | (* S0_x2=24m, S0_y2=7m *) net b (b1, b2, b3); |
| - | (* S0_x0=30m, S0_y0=-3m, S0_x2=25m, S0_y2=-3m *) net c (c0, c2, c3); | + | (* S0_x1=30m, S0_y1=-3m, S0_x3=25m, S0_y3=-3m *) net c (c0, c2, c3); |
| `elsif __PC0__ | `elsif __PC0__ | ||
| - | (* PC0_x0=-5m, PC0_y0=0m, PC0_x1=0m, PC0_y1=0m *) net a (a0, a1); | + | (* PC0_x1=-5m, PC0_y1=0m, PC0_x2=0m, PC0_y2=0m *) net a (a0, a1); |
| - | (* PC0_x1=24m, PC0_y1=7m *) net b (b1, b2, b3); | + | (* PC0_x2=24m, PC0_y2=7m *) net b (b1, b2, b3); |
| - | (* PC0_x0=30m, PC0_y0=-3m, PC0_x2=25m, PC0_y2=-3m *) net c (c0, c2, c3); | + | (* PC0_x1=30m, PC0_y1=-3m, PC0_x3=25m, PC0_y3=-3m *) net c (c0, c2, c3); |
| `else | `else | ||
| net a (a0, a1); | net a (a0, a1); | ||