Recursive paramset

A paramset permits the recursive definition of component models.

In this example we analyse a chain of RC lowpass filters whithout having to type it out explicitly. some typing.

First, define two modules as follows.

module tln0(a, b);
  parameter r;
  parameter c;
  resistor #(.r(r)) r(a b);
  capacitor #(.c(c)) c(b, 0);
endmodule

module tln1(a, b);
  parameter length
  parameter r;
  parameter c;
  resistor #(.r(r)) r(a i);
  capacitor #(.c(c)) c(i, 0);
  tln #(.length(length - 1) .c(c) .r(r)) t(i, b);
endmodule

The first one is easily seen to be an RC. The second one has an additional parameter “length”, it defines an RC followed by a “tln” of length one less. In Verilog, we can define how tln maps to one of the two, depending on the length parameter value only. We do this as follows.

paramset tln tln1
  parameter length from [2:999];
  parameter r;
  parameter c;
 .length = length;
 .r = r;
 .c = c;
endparamset

paramset tln tln0
  parameter length from [1:1];
  parameter r;
  parameter c;
 .r = r;
 .c = c;
endparamset

Note that both paramsets define a component by the same name “tln”. The simulator will evaluate the “length” parameter and pick the right one.

We define and instanciate a main circuit.

module main(1 2);
  parameter len=10
  tln #(.length(len) .c(1/len) .r(1/len)) t1(1, 2);
endmodule

main #() m(1 2);

Then we switch to spice mode, build some test circuit, and run a simulation.

spice
.options noinsensitive

V1 1 0 sin amplitude=1 frequency=1
R1 2 0 1

.print tran v(nodes)
.tran 5 > tln.out
.status notime
.end

Note how the actual number of nodes in the circuit is reported by the status command. Try a different value for length, look at the node number, and observe how the output transient changes.